We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59823

Table 3-1 of (UG933) VCCO per bank information


Under table 3-1 of (UG933), there is the following note:

"HRIO 47 uF capacitors can be consolidated at one 47 F per four banks"

However, looking at the specified capacitors for VCCO per bank, I do not see 47 uF. 


Those two footnotes should say that each VCCO bank needs one 47uF capacitor (even though there is no column for it), and that if VCCO banks are combined, you only need one 47uF cap per 4 combined banks.

The current rev (v1.6) of the User Guide is incorrect in that the 100uF column was supposed to be a 47uF column.
The next version of (UG933) will have this corrected.
Footnotes 4 and 5 only apply to that 47uF (currently shown as 100uF) column.

There are no 100uF caps actually required for VCCO banks.
You can see in the Artix table in (UG483) that the VCCO has a 47uF cap column and no 100uF one.
AR# 59823
Date 03/24/2015
Status Active
Type General Article
  • Zynq-7000
Page Bookmarked