How can I set input delay when MMCM is used on the clock path?
In general, the reference clock used for the -clock option of set_input_delay is the one created on the FPGA clock input pad.
If there is an MMCM on the clock path, the input path becomes a CDC (Clock Domain Crossing) path because the source clock (master clock) and destination clock (generated clock) are different.
In this case, you may need to add set_multicycle_path to adjust the path requirement or use a virtual clock as the reference clock, or both.
In the following example, the clk frequency is 100Mz, min input delay is 1ns and max input delay is 2ns.
If the MMCM's phase shift is negative or zero and the MMCM output clock is 100Mz, you can constrain the interface with the below constraints.
# Create clock on the clock input pad and use it as reference clock in set_input_delay
create_clock -period 10.000 -name clk [get_ports clk]
set_input_delay -clock clk -max 2.000 [get_ports datain]
set_input_delay -clock clk -min 1.000 [get_ports datain]
Note: For a negative phase-shift, a Multi-cycle constraint is typically not needed to counter balance the effect of the phase-shift.
An exception occurs if the phase-shift is so large that the clock launch or capture edges must be adjusted to keep realistic setup and hold requirements.
If the MMCM's phase shift is positive and the output clock is 100Mz, you need to add a set_multicycle_path constraint based on the original constraints to adjust the clock edge to be checked and the path requirement.
set_multicycle_path 2 -from [get_ports datain]
Note: In this case, it is not necessary to modify the hold relationship with an
additional set_multicycle_path constraint because it is already properly
established relative to the setup relationship and all rising clock edges are
active.
If the MMCM has no phase shift and the output clock is 60Mz
You can make use of a virtual clock in this case.
# Create clock on the clock input pad
create_clock -period 10.000 -name clk [get_ports clk]
# Create virtual clock and use it as the reference clock in set_input_delay
create_clock -name clk_port_vclk -period 16.67 set_input_delay -clock clk_port_vclk -max 2 [get_ports datain]
set_input_delay -clock clk_port_vclk -min 1 [get_ports datain]
AR# 59893 | |
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Date | 04/24/2014 |
Status | Active |
Type | General Article |
Tools |