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AR# 59900

Xilinx PCI Express Solutions - Post Synthesis/Implementation Netlist Functional/Timing Simulation Support

Description

Vivado Version: 2013.4
This Answer Record is applicable to all four cores below:

1. Virtex-7 FPGA Gen3 Integrated Block for PCI Express       (Xilinx Answer 54645)
2. 7 Series Integrated Block for PCI Express                           (Xilinx Answer 54643)
3. AXI Bridge for PCI Express                                                      (Xilinx Answer 54646)
4. UltraScale FPGA Gen3 Integrated Block for PCI Express (Xilinx Answer 57945)

Post Synthesis/Implementation Netlist Functional/Timing Simulation for the above cores is not currently supported.

Solution

This is a known issue and is scheduled to be fixed in a future release of the cores.

Revision History:
04/16/2014 - Initial Release
AR# 59900
Date Created 03/21/2014
Last Updated 04/16/2014
Status Active
Type Known Issues
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
  • AXI PCI Express (PCIe)
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)