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AR# 59939

Vivado Constraints - Vivado and ISE test designs with examples of IO Timing Constraints Templates


This answer record provides a Vivado test design with set_input_delay and set_output_delay constraint examples.

These examples are organized to correspond to the input delay and output delay constraints templates in Vivado.

An ISE project of the same design is also attached to demonstrate the corresponding OFFSET IN and OFFSET OUT constraints and the path analysis in ISE.
The Vivado project is compatible with 2013.4 version and the ISE project is compatible with ISE 14.7 version.


In the Vivado project, run the report_io_timing.tcl script to report timing path analysis for each constraint.
In the ISE project, run "Analyze Post-Place & Route Static Timing" under default settings to generate the timing report.

For the setup and hold analysis of each path, the ISE slack and Vivado slack have 0.004/0.005ns or 0.010/0.011ns difference.

This is expected.

The difference comes from the Total System Jitter calculation for input and output paths in the Clock Uncertainty.
In Vivado, Total System Jitter = (SJ2 + SJ2)1/2 
In ISE, Total System Jitter = (SJ2)1/2 = SJ

This is because Vivado takes both source and destination into account.

ISE however, only counts the destination for input paths and the source for output paths.

See also (Xilinx Answer 59944).



Associated Attachments

AR# 59939
Date 02/17/2015
Status Active
Type General Article
  • Vivado Design Suite
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