AR# 59946


UltraScale FPGA Gen3 Integrated Block for PCI Express v3.0 - PERSTn signal usage for Virtex Ultrascale devices


Version Found: 3.0
Version Resolved and other known issues: (Xilinx Answer 57945)

When generating UltraScale FPGA Gen3 Integrated Block for PCI Express core, the 'Use the dedicated PERSTn' option is disabled.

However, it is enabled in the core configuration GUI for Kintex UltraScale devices.

What does this option do? What is the implication of disabling this option in my design?


The default generation of the core for Virtex UltraScale devices will not use the dedicated route between the PERSTN0 package pin and the sys_reset solution IP input.

The reset input pin for the X0Y0 core will still be locked to the PERSTN0 package pin.

Since the dedicated route between the PERSTN0 packet pin and the sys_reset input pin to the core is not enabled, it will allow users to move the reset pin without causing an error in 2014.1.

While it will not cause an error, the users should not do this, because in a future release of the core the dedicated route between the PERSTN0 package pin and the solution IP sys_reset will be enabled by default.

At that point, users who have moved the reset pin will get errors in their design during place and route.

It should also be noted that the dedicated routing is specifically important for achieving maximum efficiency when using Tandem Configuration solutions.  

Use of the dedicated route reduces the number of configuration frames required for the first stage functionality and therefore reduces the size of the first stage bitstream. 

It is highly recommended to use the dedicated PERSTN package pins in the designs if possible.

Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
04/16/2014 - Initial Release
AR# 59946
Date 07/22/2014
Status Active
Type Known Issues
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