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AR# 59948

UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact.

Description

Version Found: DDR4 v5.0, DDR3 v5.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

For DDR3 and DDR4 designs, the clock port of dbg_hub should be connected to the MIG dbg_clk.

However, in some cases, the clock port of the dbg_hubmodule is incorrectly connected to ui_clk instead of dbg_clk.

When ui_clk is connected to the dbg_hub clk port, there ight be a negative timing impact on the MIG design when the debug hub module is placed far away from the MIG module.

Solution

To work around this issue, the following changes need to be made to MIG generated designs:

1) Declare dbg_clk as a wire in ./sources_1/imports/<core_name>/rtl/ip_top/example_top.v:

wire                dbg_clk;

2) Connect wire dbg_clk to dbg_clk port of MIG IP top instance:

.dbg_clk                                    (dbg_clk)

3) Add the following constraint to the top-level XDC (i.e. example_design.xdc for MIG generated designs):
connect_debug_port dbg_hub/clk [get_nets dbg_clk]

Revision History: 

4/16/14 - Initial Release


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 59948
Date 12/21/2017
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1
IP
  • MIG UltraScale
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