Version Found: MIG v5.0
Version Resolved: See (Xilinx Answer 58435)
For DDR3 and DDR4 designs, the clock port of dbg_hub should be connected to the MIG dbg_clk.
However, in some cases, the clock port of the dbg_hub module is incorrectly connected to ui_clk instead of dbg_clk.
When ui_clk is connected to the dbg_hub clk port, there may be a negative timing impact on the MIG design when the debug hub module is placed far away from the MIG module.
To work around this issue, the following changes need to be made to MIG generated designs:
1. Declare dbg_clk as a wire in ./sources_1/imports/<core_name>/rtl/ip_top/example_top.v
2. Connect wire dbg_clk to dbg_clk port of MIG IP top instance
.dbg_clk (dbg_clk)3. Add the following constraint to the top-level XDC (i.e. example_design.xdc for MIG generated designs)
connect_debug_port dbg_hub/clk [get_nets dbg_clk]
4/16/14 - Initial Release