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AR# 59961

Virtex-7 FPGA Gen3 Integrated Block for PCI Express - PCISIG Compliance Testing


Version Found: v3.0
Version Resolved and other Known Issues: See (Xilinx Answer 54645)

Following issues have been observed during a test for the PCISIG compliance workshop:

1. RxJitter Test with Tektronix: An issue has been observed during this test. This problem does not occur with other vendors used by PCISIG (Agilent or Teledyne Lecroy).  Customers who see issues with Tektronix may request to test with one of the other vendors if they fail.  The PCISIG considers a pass on any of these vendors to be valid for compliance. 

2. PCIeCV Speed Change Test: An issue has been observed during the PCIeCV speed change test on the X79 machine that PCISIG uses for testing.

3. PTC L1 Test: cfg_power_state_change_ack should be set to '1'.

4. Transmitter Testing for PCIe 3.0: An updated TXPOSTCURSOR_10  value is needed to pass this test.

This answer record provides a patch that fixes both these issues.


Please follow the instructions below to install the patch.

Note: The provided patch is for 2013.4 Vivado tool version.

Open the Vivado tool -> IP Catalog

1.    Generate a 7 series Gen3 Integrated Block for PCI Express core

2.    In example_design source area:
    Replace these files
    a.    pcie3_7x_0_gt_top.v
    b.    pcie3_7x_0_pipe_wrapper.v
    c.    pcie3_7x_0_pipe_eq.v
    d.    pcie3_7x_0_rxeq_scan.v

3. Set cfg_power_state_change_ack to '1' in xilinx_pcie_3_0_7vx.v. This is the example design top level wrapper. Users should make this change in their top level wrapper.

4.    For the Tektronix RxJitter test issue, do the following:
    a.    The RXJITTER_TEK - Loopback test attribute is set to FALSE by default in pcie3_7x_0_gt_top.v.
    b.     Set it to be TRUE for Tektronix RxJ testing.
    Note: The above change is not required for PCIeCV Speed Change Test.

5. For Transmitter Testing for PCIe 3.0:

In pipe_eq.v file

Change the following: 

localparam          TXPOSTCURSOR_10 = 6'd25;
localparam          TXPOSTCURSOR_10 = 6'd28;

This will be fixed in a future release of core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
04/02/2014 - Initial Release
04/03/2014 - Added update for Transmitter Testing for PCIe 3.0


Associated Attachments

Name File Size File Type
Xilinx_PCISIG_patch.zip 33 KB ZIP
AR# 59961
Date 05/01/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2013.4
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)