eMMC Memory timing is defined by the JEDEC standard version 4.41.
in accordance with this specification, the minimum input hold time required is 3 ns (referenced to the rising edge of the clock). However, the Zynq-7000 SDIO Controller has a min clock to out delay (all outputs) of 2 ns.
If the controller is used in High Speed Mode (Zynq-7000 data output on rising edge of the clock) the hold time requirement for the JEDEC/MMC 4.41 Specification is NOT met (*).
In Standard Speed Mode (Zynq-7000 data output on falling edge of the clock) an extra half clock period is added to the clock to out delay meeting the hold time requirement (*).
NOTE (*): Assuming all trace lengths are matched.
Xilinx tested the functionality of the Zynq-7000 SDIO Controller using a Micron MTFC4GMVEA-1M (eMMC device).
Both Standard Speed (25MHz) and High Speed (50MHz) Modes in Single Data Rate (SDR) have been successfully functionally tested but the Zynq-7000 SDIO Controller operated in High Speed Mode is NOT compliant with the JEDEC standard 4.41 for eMMC.
Xilinx recommends the user to contact the eMMC Vendor directly and request the actual hold time requirement for their eMMC memories (usually an NDA document).
Without this characterization data Xilinx recommends to use eMMC with the Zynq-7000 SDIO Controller only in Standard Speed Mode (max frequency of 25MHz).
A possible work-around is to add the additional 1ns delay in the board layout:
The user needs to increase the length of data and command lines by 1000 ps /(150 ps/inch) = 6.67 inch relative to the clock line.
(NOTE: assuming a delay of 150 ps/inch).
The addition of delay will ensure hold time for the controller is met.
The addition of delay will require the following equation to be satisfied when the SDIO controller is receiving data:
20ns (Tsd,device,cko, max + 1ns) >=Setup requirement for Zynq controller, considering 50 MHz clocking mode.
Tsd,device,cko, max implies max clock to out delay of the device.
=>16>= Tsd,device,cko,max, considering Setup requirement for Zynq as 3 ns.
This implies max clock to output delay should be 16 ns for the eMMC device.