This is a limitation of the Data Width Converter.
In this design, the 64 bit Master and 32 bit Slave are connected via AXI Interconnect and the Data Width Converter is used.
to save logic, the Data Width Converter supports only single thread ID, so it does not have ID signals in MI.
(PG059) AXI Interconnect Product Guide v2.1 states:
The Data Width Converter allows multiple outstanding transactions to be propagated.
Transaction characteristics from the AW/AR channel transfers are queued while awaiting corresponding response transfers.
However, due to the possibility of write response and read data re-ordering, transactions issued on the MI side of the Data Width Converter are restricted to a reordering depth of 1 (single ID thread).
As a result, the currently active transaction ID is stored internally and no ID signals are present on the MI.
This eliminates the need for downstream IP cores to store and process ID information, saving logic.
Due to this restriction, even if the master and slave are capable of multi-threading, the slave always receives a single thread (ID=0) from AXI Interconnect (when it includes the data width converter) and never responses in re-order.