wire [45:0] io_i = 46'd0; assign io_i = io;
Critical Warning : [Synth 8-3352] multi-driven net <signal_name> with 1st driver pin '<pin_name1>' [xxx.v.3] Critical Warning : [Synth 8-3352] multi-driven net <signal_name> with 2nd driver pin '<pin_name2>' [xxx.v.3]
The problem is due to the difference between a reg declaration and a wire declaration in Verilog.
When you have a declaration of type reg that looks like :
reg my_signal = initial_value;
This is treated as an initial condition.
However if you have a statement that looks like :
wire my_signal = initial_value;
This is treated as a continuous assign statement and not an initial condition.
So if there is another assign statement for my_signal, you will get multi-driven critical warnings.
The solution is to modify your RTL.