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AR# 60015

Vivado Synthesis - ERROR: [Synth 8-550] port width mismatch in instance array for port 'din[a]'


The following usage of instance array in System Verilog causes an error in Vivado Synthesis.

Example code:

typedef enum logic [1:0] {s0, s1, s2, s3} enum_t;
typedef struct packed {
  logic [7:0] a;
  enum_t x;
  logic b;
} struct_t;
module top (
            input struct_t din [1:0],
            input struct_t dout [1:0]
struct_t din_0,din_1;
struct_t dout_0,dout_1;
sub u[1:0] (
assign din_0 = din[0];
assign din_1 = din[1];
assign dout[0] = dout_0;
assign dout[1] = dout_1;
module sub (
            input struct_t din,
            output struct_t dout
assign dout = din;

Vivado Synthesis is not able to resolve the port width mapping in the instance array when accessing the structure.

ERROR: [Synth 8-550] port width mismatch in instance array for port 'din[a]': actual width = 22, formal width = 8, instance count = 2  [XX/top.sv:36]


Support for the structure type of port map in an instance array has been added in Vivado 2017.3.

AR# 60015
Date 01/05/2018
Status Active
Type Known Issues
  • Vivado Design Suite
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