Version Found: v3.0 (Rev1)
Version Resolved and other Known Issues: See (Xilinx Answer 54645)
When implementing the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v3.0 (Rev1) core in either of the two Tandem Modes, the tool gives the following warning message if the "report_drc -ruledeck timing_checks" command is issued.
This warning is issued because the ASYNC_REG attribute is only applied to the first of two clock domain crossing registers.
While this produces the desired effect in the generated netlist, both registers should have the ASYNC_REG attribute applied to them.
While no action is required, the warning message can be eliminated by applying the ASYNC_REG property to the identified registers in the user constraints file.
The command to apply this constraint for the example above is shown below.
set_property ASYNC_REG TRUE [get_cells c_i_wrapper_support_i/c_i_wrapper_i/c_i_i/c_inst/inst/inst/c_i_c_inst_0_fast_cfg_init_cntr_i/cdc_reg2_reg]
This will be fixed in a future release of the core.
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
04/26/2014 - Initial Release