Title: Use of GTY transceivers limited to behavioral HDL simulation.
This release adds 'start from scratch' and additional preset configuration options for GTY transceivers in Virtex UltraScale devices, but all GTY configurations are limited to behavioral HDL simulation at this time.
Synthesis and implementation of GTY configurations are not yet possible in Vivado 2014.1, and result in implementation issues including the synthesis message below:Work-around: NA
To Be Fixed: 2014.2
Status: Resolved in 2014.2 (for use with core v1.3)
Title: Unsupported programmable divider causes core generation error.
Description: Some low line rate, wide data width Wizard configurations result in the inferred use of a currently-unsupported programmable divider setting, producing the following core generation error message:
For your low line rate configuration, please choose narrower internal and external data widths.This same error may also occur as a result of enabling the selectable TXOUTCLK frequency feature and choosing a low-frequency TXOUTCLK value.
Work-around: Choose narrower user and internal data width options.
If using the selectable TXOUTCLK frequency option, choose a higher-frequency value.
To Be Fixed: Future release
Status: Resolved in 2014.4 core v1.4 Rev1
Title: Wiring error in user data width sizing helper block for GTY transceivers utilizing the 160-bit RX user data width only.
Description: The receiver module of the user data width sizing helper block has a wiring error that is present only when a GTY transceiver is targeted and the 160-bit RX user data width is selected.
This issue does not affect any configurations using GTH transceivers, nor does it affect configurations using GTY transceivers that use RX user data widths other than 160 bits.
Work-around: Select a different RX user data width.
If 160 bits are required, locate the user data width sizing helper block in the example design and do not use it at this time.
To Be Fixed: 2014.2
Status: Resolved in 2014.2 core v1.3
Title: Reset controller helper block input gtwiz_reset_all_in may reset TX and RX resources in parallel.
The Wizard reset controller helper block input gtwiz_reset_all_in is designed to reset TX resources, followed by RX resources, in sequence.
An issue with bit synchronization delay variability can result in TX resources instead being reset in parallel with RX resources.
For configurations where TX must be reset before RX for stability reasons (for example, when operating in loopback), use of the following work-around is recommended.
Work-around: Tie or drive the gtwiz_reset_all_in input low, and utilize other reset controller helper block inputs to perform the equivalent sequential reset procedure.
For example, in sequence:
1. Pulse gtwiz_reset_tx_pll_and_datapath_in
2. Wait for the rising edge of gtwiz_reset_tx_done_out
3. Pulse either:
a. gtwiz_reset_rx_datapath_in (if TX and RX data paths use the same PLL), or
b. gtwiz_reset_rx_pll_and_datapath_in (if TX and RX data paths use different PLLs)
4. Wait for the rising edge of gtwiz_reset_rx_done_out
To Be Fixed: 2014.3
Status: Resolved in 2014.3 core v1.4
Title: Receiver termination voltage limited to FLOAT for DC coupled links.
Description: Wizard configurations which use DC link coupling must choose FLOAT for receiver termination.
This selection is available but is not currently enforced by the Wizard.
Work-around: When customizing the Wizard core instance in the GUI, select FLOAT for the Termination field in the Receiver: Advanced section of the first tab.
To Be Fixed: 2015.3
Status: Resolved in 2015.3 core v1.6
Title: GTH CPLL reset disrupts TXOUTCLK in some UltraScale engineering sample devices.
Description: In GTH configurations targeting Kintex UltraScale ES1/ES2 and Virtex UltraScale ES1 engineering sample devices, resetting the CPLL will disrupt the TXOUTCLK signal, even when the CPLL is used for the RX data path and a QPLL is used for the TX data path.
This is due to the presence and operation of the CPLL calibration procedure which briefly takes control of the TXOUTCLK source during CPLL reset, irrespective of which resources the CPLL clocks.
Work-around: This behavior cannot be avoided in GTH configurations targeting the affected engineering sample devices.
If runtime disruption to TXOUTCLK in response to resetting the CPLL is not tolerable in configurations where the CPLL drives only RX resources, you will need to reset and achieve lock on the CPLL prior to, or separate from bringing up TX resources.
Note: This limitation has been added to the UltraScale FPGAs Transceivers Wizard Product Guide (PG182) v1.6.