We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
Bitstream generation for the GTP example design fails with following DRC Error message:
ERROR: [Drc 23-20] Rule violation (REQP-1584) GT PLLLOCKDETCLK can not be REFCLK - GTPE2_COMMON pin u_ibert_core/inst/QUAD.u_q/u_common/u_gtpe2_common/PLL0LOCKDETCLK cannot be driven by a clock derived from the same clock used as the reference clock for the PLL, including TXOUTCLK*, RXOUTCLK*, the output from the IBUFDS_GTE2 providing the reference clock, and any buffered or multiplied/divided versions of these clock outputs. Please see UG482 for more information. Source, through a clock buffer, is the same as the GT cell reference clock.
To work around this issue, set the Vivado Synthesis option -flattern_hierarchy to 'none' before running synthesis.
This is a known issue which will be addressed in a future release.