Version Found: v5.0
Version Resolved: See (Xilinx Answer 69038)
For MIG UltraScale QDRII+ 36-bit designs using x18 components, it is possible that the clk_from_ext_upp and clk_from_ext_low parameter values will be incorrect.
This can result in the following CRITICAL WARNING being received during implementation:
CRITICAL WARNING: [Route 35-54] Net: u_my_mig/inst/u_qdriip_phy/phycal/phy/byteWrap[2].u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clk_to_ext_south_low is not completely routed.
To resolve this the following changes to the clk_from_ext_upp and clk_from_ext_low parameters should be made inside ./sources_1/ip/<core_name>/rtl/map/phy_clk_map.vh:
Revision History
04/16/2014 - Initial release
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
69038 | UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues | N/A | N/A |