AR# 60047

UltraScale/UltraScale+ QDRII+ IP - Incorrect parameter values for 36-bit designs using x18 components

Description

Version Found: v5.0

Version Resolved: See (Xilinx Answer 69038)

For MIG UltraScale QDRII+ 36-bit designs using x18 components, it is possible that the clk_from_ext_upp and clk_from_ext_low parameter values will be incorrect.

This can result in the following CRITICAL WARNING being received during implementation:

CRITICAL WARNING: [Route 35-54] Net: u_my_mig/inst/u_qdriip_phy/phycal/phy/byteWrap[2].u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clk_to_ext_south_low is not completely routed.

Solution

To resolve this the following changes to the clk_from_ext_upp and clk_from_ext_low parameters should be made inside ./sources_1/ip/<core_name>/rtl/map/phy_clk_map.vh:

,.clk_from_ext_low (
  {
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  clk_to ext_north_low[2]
  1'b1,
  1'b1,
  clk_to_ext_south_low[1]
}
)
,.clk_from_ext_upp (
  {
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  1'b1,
  clk_to ext_north_upp[2]
  1'b1,
  1'b1,
  clk_to_ext_south_upp[1]
}
)

Revision History
04/16/2014 - Initial release

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
69038	UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues	N/A	N/A

AR# 60047
Date	02/02/2018
Status	Active
Type	Known Issues
Devices	Kintex UltraScale Virtex UltraScale Kintex UltraScale+ More Virtex UltraScale+ Zynq UltraScale+ MPSoC Less
Tools	Vivado Design Suite Vivado Design Suite - 2014.2
IP	QDRII+ SRAM

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