Vivado 2013.4 - IBERT completes the Implementation with timing errors when the device is Artix-7 and the datarate is high.
For example IBERT with 6.25G lanes speed on Artix-7 xc7a200tffg1156-2.
This has been reported in Vivado 2013.4 and previous releases.
In particular, the default implementation completes with timing errors.
In this case trying a different implementation strategy will help.
Please follow the steps below in order to select a new strategy for the next implementation run.
1) In the design runs window, add a new implementation.
2) Select "implementation" run.