We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60079

2013.3 Vivado Synthesis - constant logic signals connected to Debug cores in the HDL are not preserved


In the code below, the "p_in" and "p_out" signals are assigned constant values and connected to an ILA core.

In Vivado 2013.3, these net names are not preserved but changed to const0 and const1 in the synthesized netlist, and mark_debug properties are not attached to these nets. 

wire [7:0] p_in;
wire [7:0] p_out;
assign p_in = 8'b10101010;
assign p_out = 8'b01010101;
    ila2 ila2_1 (


This issue is not seen in 2013.4 and newer versions.

If you do experience this issue, the workaround is to manually apply mark_debug to the signals in HDL.
(*mark_debug = "true"*)assign p_in = 8'b10101010;
(*mark_debug = "true"*)assign p_out = 8'b01010101;
AR# 60079
Date 04/16/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2013.3
Page Bookmarked