This is expected.
Even though "-flatten_hierarchy" is set to none, Vivado Synthesis automatically enables the rebuilt flow before I/O insertion when there are tri-state buffers/cells in the lower level modules.
This is to move the tri-state logics to top level.
You would see the following message in Synthesis report:
design has tricells in submodule, set to rebuild hierarchy flow
When the hierarchy is re-built, the module interface may not be exactly the same as in RTL.
If you want to preserve the exact design hierarchy, move the Tri-state buffers from submodules to the top level.