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AR# 60104

Vivado Synthesis - FSM is not inferred where state register is assigned with a signal (non-constant)

Description

Vivado Synthesis does not infer any FSM from the following example code in which the state register is assigned with a signal (non-constant).

type state     is  (state00, state01, delay);
signal STATE_REG    : state := state00;
signal STATE_AFTER_DELAY    : state := delay;
seq_assign:    process(clk,rst)
......
      case STATE_REG    is
      ......
      when delay =>
          STATE_REG    <= STATE_AFTER_DELAY;
......

Solution

Vivado Synthesis does not support FSMs where the state register is assigned with a non-constant signal.
AR# 60104
Date Created 04/03/2014
Last Updated 06/06/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite