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AR# 60156

Spartan-6 ICAP Component Switching Limit violation


According to the datasheet DS162, there are two possible maximum frequencies for the ICAP.

The difference depends on the read back process.

For parts smaller than LX100 and non-1L speed:

  • 20 MHz max when BRAMs are read back.
  • 50 MHZ max when no BRAMs are read back.

Is it safe to ignore the Switching Limit Violation if there is no intention to read back from the RAMs?

Slack: -30.000ns (period - min period limit) 
Period: 20.000ns 
Min period limit: 50.000ns (20.000MHz) (Tcapper) 
Physical resource: s6multiboot/icaps6/CLK 
Logical resource: s6multiboot/icaps6/CLK 
Location pin: ICAP_X0Y0.CLK 
Clock network: clk50


In some cases it is safe to ignore this Switching Limit Error. 

This only applies if there is no intention to read back from the BRAM modules.

These situations occur when using the SEM IP core and a POST_CRC process is going to be executed with the ICAP.


The speed files include the Switching Limitation for each component, however, they do not include the differences for ICAP module without read back from BRAM.

As a result, the tool uses the worse case scenario: 20 MHz.

Because there are no future plans for S6 devices, those speed files will not be updated.

AR# 60156
Date 12/19/2014
Status Active
Type General Article
  • Spartan-6
  • ISE Design Suite
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