General Description: When I compile the .v Verilog behavioral models extracted by get_models from the CORE Generator tree, error messages similar to the following are reported from MTI:
"C_REG_FD_V1_0 already exists"
Although these are flagged as errors, the messages are harmless and merely indicate that the same lower-level module is referenced by more than one higher-level macro in the CORE Generator Verilog behavioral simulation library. They do not mean that the models were not compiled properly.
If you wish to avoid these errors, you can compile the models using individual MTI "vlog" commands. The models should be compiled in the following order for the C_IP4 release: