I have created an IPI subsystem which contains an "AXI Interconnect IP" with a default name of "axi_interconnect_0".
I used this subsystem to integrate with another "AXI Interconnect IP" in a new Block Diagram, (BD), but I receive critical warnings that the IPs files are being overwritten.
Why does this occur? How can I avoid this?
This is a known issue which occurs because the default names for the IP are the same in the subsystem and in the Block Design where the new "AXI Interconnect IP" is included.
Both cores are called "axi_interconnect_0" and as such one is overwritten.
In the future it will be possible to avoid this as the "Out-Of-Context" flow will be enabled for IPI designs.
The current work-around for this issue is to rename one of the IP cores.