We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60213

Vivado Synthesis - LOC constraint applied in RTL on ports that are vectors is not supported


When setting the LOC constraint in RTL on a port that is a vector instead of a bit, the LOC constraint is not used.  

For example :

my_input_bit : in std_logic;
my_input_vector : in std_logic_vector(1 downto 0);

In cases where attribute LOC of my_input_bit is "K13"; it will work.
In cases where attribute LOC of my_input_vector is "K14,K15"; it will not work.


This reason that this does not work is that the tool is unsure what should get forward annotated. 

The meaning of this is ambiguous. 

Since this attribute is just passed along to the back end, does it mean that "K14,K15" should be passed to both my_input_vector(1) and my_input_vector(0), or should the tool parse the string and give K14 to my_input_vector(1) and K15 to my_input_vector(0)?

For this reason, this coding style is not supported in RTL. 

The workaround is to use the XDC file to set LOC constraints instead.

AR# 60213
Date 06/06/2014
Status Active
Type Known Issues
  • Vivado Design Suite