In my design, I have an output register within a submodule with a KEEP attribute attached to it.
The Input/Output Block (IOB) property is set to the output port via XDC but it is not honored.
The following critical warning occurs and the Flip-flop (FF) ends up in SLICE.
[Place 30-722] Terminal 'XX' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O
From a synthesized design, a dummy LUT1 is inserted between the FF and OBUF due to the KEEP attribute, as otherwise the net name will be lost.
However, opt_design is able to remove the LUT1 and the IOB property is successfully propagated to the register.
Even if I manually lock down the register to OLOGIC site, the LOC constraint cannot be obeyed.
A different critical warning is seen.
[Vivado 12-2285] Cannot set LOC property of instance 'xxx', loc is blocked
Why is the register prevented from being placed into IOB?