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AR# 60269

2014.1 Vivado - create_generated_clock is not accepted by synthesis. Incorrect set of required parameters for "create_generated_clock"

Description

The constraint below can be used to rename auto-derived generated clocks.

create_generated_clock -name <name> <object>

However, this command is not accepted by synthesis in Vivado Design Suite 2014.1.

If the constraint is used, the below message appears in the synthesis report file.

incorrect set of required parameters for "create_generated_clock" at line 2 of file /proj/project_20.xpr/project_20/project_20.srcs/constrs_1/new/abc.xdc

---------------------------------------------------------------------

Usage:

create_generated_clock

[-help]

[-name <String>]

[-source <List>]

[-edges <List>]

[-divide_by <Int>]

[-multiply_by <Int>]

[-edge_shift <List>]

[-duty_cycle <Float>]

[-invert]

port_pin_list

[-add]

[-master_clock <List>]

[-combinational]

[{>|>>} <stdoutFile>]

Solution

This issue will be fixed in release 2014.2. 

In Vivado 2014.1, the create_generated_clock constraint is not being processed correctly during synthesis. 

Avoid renaming clocks using create_generated_clock in synthesis XDC.

AR# 60269
Date Created 04/13/2014
Last Updated 06/04/2014
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2014.1