This Release Note is for the High Speed SelectIO Wizard v1.0 released in Vivado 2014.1 and contains the following information:
The High Speed SelectIO Wizard v1.0 supports the Xilinx UltraScale FPGAs.
The High Speed SelectIO Wizard created a HDL file (Verilog) that contains I/O and clocking logic such as RX/TX_BITSLICE_CONTROL and PLLE3 blocks customized to the users interface requirements.
Pin LOC update in this wizard updates the RTL to provide required connectivity among blocks.
V1.0 is the initial release of this wizard.
New Features in v1.0
Bug Fixes in v1.0
Known Issues in v1.0
High Speed SelectIO Wizard v1.0 core in 2014.1 will fail in simulation for clk_src = EXTERNAL when data width other than 1 is selected. This is a simulation model issue.
Workaround: Switch to clk_src = PLL
High Speed SelectIO Wizard v1.0 core in 2014.1 will not work when RX DELAY CASCADE is true. This is a simulation model issue.
Workaround: No workaround. Users cannot use this feature.
High Speed SelectIO Wizard v1.0 core in 2014.1 will have a TIMING=17 Warning. This may impact the performance on Hardware.
Workaround: No workaround.
15/04/14 - Initial Release