This is a known issue to be fixed in a future release of the core. To workaround the issue, make the following changes in your top level file.
In the out of the box default example design, this change should be made in the synth/pcie3_ultrascale_0.v file.
The "Version Found" column lists the version the problem was first
discovered. The problem also exists in earlier versions, but no specific
testing has been performed to verify earlier versions.
04/16/2014 - Initial Release