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AR# 60299

UltraScale FPGA Gen3 Integrated Block for PCI Express v3.0 - The host system fails to detect PF1

Description

Version Found: 3.0
Version Resolved and other known issues: (Xilinx Answer 57945)

If the UltraScale FPGA Gen3 Integrated Block for PCI Express v3.0 core is configured by enabling both PF0 and PF1, the host system successfully detects PF0 but not PF1.

Solution

This is a known issue to be fixed in a future release of the core. To workaround the issue, make the following changes in your top level file. 

From:

TL_PF_ENABLE_REG("TRUE"),

To:

TL_PF_ENABLE_REG(2'b01),

In the out of the box default example design, this change should be made in the synth/pcie3_ultrascale_0.v file.

Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
04/16/2014 - Initial Release

AR# 60299
Date Created 04/15/2014
Last Updated 04/18/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)