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  3. AR# 60305: Memory Interface UltraScale DDR4/DDR3 - Hardware Debug Guide

AR# 60305

Memory Interface UltraScale DDR4/DDR3 - Hardware Debug Guide

Description

This answer record provides a downloadable MIG UltraScale DDR4/DDR3 Hardware Debug Guide in PDF format to enhance its usability.  

The download should be used through Vivado 2015.2.  Starting with Vivado 2015.3, the debug documentation is included within PG150.  Please reference the Debugging section.

Answer records are Web-based content that are frequently updated as new information becomes available.

Visit this answer record to obtain the latest version of the PDF.


Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).

The Xilinx MIG Solution Center is available to address all questions related to MIG.

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Please download the MIG UltraScale DDR4/DDR3 Hardware Debug Guide (PDF) attached to the end of this solution.

This document describes techniques to debug calibration failures and data errors related to designs using the MIG UltraScale DDR4/DDR3 SDRAM core. 

A complete list of signals to analyze when debugging calibration failures and data errors has been provided as well as information on how to interpret the results to find the root cause of the issue at hand.


Revision History:
10/03/14 - Initial Release
12/08/14 - 2014.4 Release
04/30/15 - 2015.1 Release
07/01/15 - 2015.2 Release
11/05/15 - 2015.3 Release

Attachments

Associated Attachments

Name File Size File Type
Xilinx_Answer_60305__2015_2.pdf 3 MB PDF
AR# 60305
Date 05/26/2017
Status Active
Type General Article
Devices
IP
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