Version Found: DDR4 v5.0
Version Resolved: See (Xilinx Answer 69035)
Internal VREF is required for all DDR4 interfaces.
See the LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150) for details.
However, the MIG tool incorrectly allows the Internal VREF option (located on the FPGA Options screen) to be deselected.
The MIG tool will correctly force Internal VREF to be enabled in the next release.
Until then, ensure that all MIG DDR4 interfaces generated have Internal VREF enabled.
Enabling Internal VREF within the tool ensures that the appropriate XDC constraints are set.
Note: the dedicated VREF pins in the banks used for DDR4 must be tied to ground with a 500 resistor.
Also, while Internal VREF is required for DDR4, it is optional for DDR3 interfaces.
04/18/2014 - Initial Release