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AR# 60347

2014.1 IPI - MIG flow for AC701 includes an incorrect clock pin

Description

Generating a MIG example design in IPI using the AC701 board flow may result in an incorrect pin out for clock outputs.
 
How can this issue be resolved?

Solution

A workaround for this issue is to lock the sys_clk_p and sys_clk_n to R3 and P3 using the following constraints:

# PadFunction: IO_L13P_T2_MRCC_34
set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_p}]
set_property PACKAGE_PIN R3 [get_ports {sys_clk_p}]

# PadFunction: IO_L13N_T2_MRCC_34
set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_n}]
set_property PACKAGE_PIN P3 [get_ports {sys_clk_n}]


This issue will be fixed in a future software release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51900 Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 60347
Date Created 04/19/2014
Last Updated 07/15/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.1
Boards & Kits
  • Artix-7 FPGA AC701 Evaluation Kit