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AR# 60356

Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates


This Design Advisory covers the required updates to the 7 Series FPGAs Transceivers Wizard version v3.2 in Vivado 2014.1 that affects GTP, GTX, and GTH transceivers.

Some of the constraints generated from the GT Wizard v3.2 or earlier need to be updated.

Below is a rundown of the edits required to <component_name>.xdc and <component_name>_ooc.xdc files.
The following updates apply when the "Include Shared Logic in Core" option is selected in page1 of the wizard.


1. For GTREFCLK, both p-side and n-side pins are constrained. Only the P-side of the buffer needs to be constrained.
The constraint for the N-side of the buffer (shown below) should be removed. This added clock will cause unnecessary propagation of clocks in the timer.

create_clock -period 6.4 [get_ports q3_clk1_gtrefclk_pad_n_in]

2. The following create_clock constraint needs to be moved to the top-level buffer. Otherwise, all of the input buffer insertion delay has been removed and will be lost for the skew analysis.

Original Constraint:
create_clock -period 16.667 [get_pins -hier -filter {name=~*gt_usrclk_source*DRP_CLK_BUFG*I}]

Required Constraint:
create_clock -period 16.667 [get_ports sys_clk_in_p]

3. False path constraints are set between DRP_CLK and TXOUTCLK. The set_false_path constraints use clock objects [get_clocks] and clock objects are part of the global namespace.
If any path between DRP_CLK and TXOUTCLK exists in the user design, these constraints will be applied on those paths also. This constraint may (or) may not be required to be applied to these paths.
Constraints to be removed:
set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt_usrclk_source*DRP_CLK_BUFG*I}]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtwizard_0_i*gthe2_i*TXOUTCLK}]]
set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtwizard_0_i*gthe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt_usrclk_source*DRP_CLK_BUFG*I}]]
If the design needs CDC paths, the requirement is that the cells of the paths are used, not the clocks themselves.


The following constraint is present in <component_name>_ooc.xdc . Since the buffer is in the design, it requires the clock constraint to be placed in <component_name>.xdc.

create_clock -period 6.4 [get_nets -hier -filter {name=~*q3_clk1_gtrefclk_pad_n_in}]
create_clock -period 6.4 [get_nets -hier -filter {name=~*q3_clk1_gtrefclk_pad_p_in}]
The following updates apply when the "Include Shared Logic in Core" option is selected in page1 of the wizard.


The GT refclk constraint references the net instead of a port.

Original Constraint:
create_clock -period 6.4 [get_nets -hier -filter {name=~*gt0_gtrefclk0_in}]

Required Constraint:
create_clock -period 16.667 [get_ports gt0_gtrefclk0_in]


The following constraint needs to be removed since the buffer is not in the IP hierarchy

create_clock -period 6.4 [get_nets -hier -filter {name=~*gt0_gtrefclk0_in}]


To resolve this issue in Vivado 2014.1, install the patch at the end of this answer record.

Refer to the readme file for instructions on how and where to install the patch files.

These issues will be resolved and this patch will no longer be required in the Vivado 2014.2 release.


Revision History:

05/26/2014 - Initial Release


Associated Attachments

Name File Size File Type
ar60356_GTwizard_v3_2_preliminary_rev1.zip 15 KB ZIP
AR# 60356
Date 05/23/2014
Status Active
Type Design Advisory
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Vivado Design Suite - 2014.1
  • 7 Series FPGAs Transceivers Wizard