AR# 60356: Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates
Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates
This Design Advisory covers the required updates to the 7 Series FPGAs Transceivers Wizard version v3.2 in Vivado 2014.1 that affects GTP, GTX, and GTH transceivers.
Some of the constraints generated from the GT Wizard v3.2 or earlier need to be updated.
Below is a rundown of the edits required to <component_name>.xdc and <component_name>_ooc.xdc files.
The following updates apply when the "Include Shared Logic in Core" option is selected in page1 of the wizard.
1. For GTREFCLK, both p-side and n-side pins are constrained. Only the P-side of the buffer needs to be constrained. The constraint for the N-side of the buffer (shown below) should be removed. This added clock will cause unnecessary propagation of clocks in the timer.
3. False path constraints are set between DRP_CLK and TXOUTCLK. The set_false_path constraints use clock objects [get_clocks] and clock objects are part of the global namespace. If any path between DRP_CLK and TXOUTCLK exists in the user design, these constraints will be applied on those paths also. This constraint may (or) may not be required to be applied to these paths.