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AR# 6037

4.1i CORE Generator, MTI, VHDL - What MTI commands are required to analyze/compile the CORE Generator VHDL models?

Description

Keywords: CORE Generator, COREGen, error, VHDL, get_models, compile, analyze

Urgency: Standard

General Description:
What ModelSim/VHDL commands are required to analyze/compile the CORE Generator VHDL models (when extracted using the "get_models" utility)?

Solution

As documented in CORE Generator User Guide, the ModelSim commands that are needed to analyze the models are:

vlib xilinxcorelib
vmap xilinxcorelib ./xilinxcorelib

vcom -work xilinxcorelib <path_to_XilinxCoreLib_SOURCE_FILE_DIRECTORY>/<name_of_vhd_file>

For example:

vlib xilinxcorelib
vmap xilinxcorelib ./xilinxcorelib

vcom -work xilinxcorelib /tools/xilinx/vhdl/src/XilinxCoreLib/prims_constants.vhd

Please refer to (Xilinx Answer 6250) for information on the order in which the models must be compiled.
AR# 6037
Date Created 03/26/1999
Last Updated 10/09/2003
Status Archive
Type General Article