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AR# 60377

14.7 Timing - Path to BUFMRCE.CE pin is not analyzed


The path from a fllip-flop (FF) to the BUFMRCE.CE pin is not analyzed under the period constraint.

The FF is driven by the same clock that is driving the BUFMRCE.I pin.

How can I force this path to be analyzed?


There is an issue in ISE Design Suite where the BUFMRCE is not resolved to be an endpoint and is not added to the associated timing group.

This issue is not seen in Vivado. 
As a workaround use the below constraints to constrain the path from the FF or IO to the BUFMRCE.CE pin.
PIN "BUFMRCE_inst.CE" TPSYNC = clkbuf_grp;
INST "FDRE_inst" TNM = ce_reg; (or INST "io_name" TNM = ce_reg;)
TIMESPEC TS_ff2ce = FROM "ce_reg" TO "clkbuf_grp" x ns;

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40716 12.1 Timing - CE pin of BUFGCE is not analyzed N/A N/A
AR# 60377
Date 10/15/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
  • ISE Design Suite - 14
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