AR# 60387

JESD204 v5.2 - Ultrascale GT wrapper for multi-lane core has incorrect connections for DRPCLK


When using a JESD204 v5.2 core ( with lanes > 1)  on  an Ultrascale device, the DRPCLK is only connected to the lane 0 Transceiver in the GT top level wrapper.

This is a known issue for the JESD204 v5.2.


 In the file jesd204_0_gtwizard_ultrascale_v1_2_top.v locate the following line:

assign drpclk_in = drpclk; 

Change this to:

assign drpclk_in = {drpclk, drpclk, };

drpclk is repeated as many times as there are lanes in the design.

for example, for a 4-lane core :

assign drpclk_in = {drpclk, drpclk, drpclk, drpclk, };

Revision History:

04/23/14 - Initial Release

AR# 60387
Date 04/25/2014
Status Active
Type Known Issues