There is no initialization of the DDR IOB registers 0XF8000B58-B6C which will result in drive strength and slew rate settings on the PS DDR I/O pins that are different than intended and characterized.
All Zynq-7000 PS DDR3/DDR3L/DDR2/LPDDR2 users are encouraged to incorporate the following fixes for increased margin and stability.
Name | File Size | File Type |
---|---|---|
ar60454_edk_14_7_preliminary_rev1.zip | 1 MB | ZIP |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
47915 | Design Advisory Master Answer Record for Zynq-7000 SoC Devices | N/A | N/A |