AR# 60454: Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier
Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier
There is no initialization of the DDR IOB registers 0XF8000B58-B6C which will result in drive strength and slew rate settings on the PS DDR I/O pins that are different than intended and characterized.
All Zynq-7000 PS DDR3/DDR3L/DDR2/LPDDR2 users are encouraged to incorporate the following fixes for increased margin and stability.
Vivado 2013.3 and earlier:
A Vivado 2014.1 or later ps7_init.tcl or ps7_init.c may be substituted.
If upgrading the entire user project is not feasible, a 2014.1 or later block diagram with only a Processing System 7 IP instance with the same IP configuration settings may be used as a donor project.
To generate the ps7_init.c and ps7_init.tcl files:
Generate the Block Design (solving any minor design rule errors as necessary), Click File-> Export Hardware for SDK, and then launch SDK.
A patch for ISE/EDK 14.7 is available:
The attached patch file addresses the following issues in EDK XPS 14.7 for Zynq-7000 devices: