UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60472

2014.1 Vivado HLS - Interval in Co-simulation report is different from C-Synthesis report.

Description

In my design, the C Synthesis report says II=28.

 
+ Latency (clock cycles):
    * Summary:
 
    +-----+-----+-----+-----+----------+
    |  Latency  |  Interval | Pipeline |
    | min | max | min | max |   Type   |
    +-----+-----+-----+-----+----------+
    |  110|  110|   28|   28| function |
    +-----+-----+-----+-----+----------+
 
However, Co-simulation reports Interval = 111.
 
+----------+----------+-----------------------------------------------+-----------------------------------------------+
|          |          |                    Latency                    |                    Interval                   |
+   RTL    +  Status  +-----------------------------------------------+-----------------------------------------------+
|          |          |      min      |      avg      |      max      |      min      |      avg      |      max      |
+----------+----------+-----------------------------------------------+-----------------------------------------------+
|      VHDL|      Pass|            111|            111|            111|            111|            111|            111|
|   Verilog|      Pass|            111|            111|            111|            111|            111|            111|
|   SystemC|        NA|             NA|             NA|             NA|             NA|             NA|             NA|
+----------+----------+-----------------------------------------------+-----------------------------------------------+
 
Looking at the simulation wave form, it looks like the testbench does not send next data even though ap_start is asserted:
 
60472_1




Solution

The II=111 from C/RTL co-simulation is calculated based on ap_start intervals (that is, how often new data is sent to the HLS module).
 

The Vivado HLS C/RTL co-simulation testbench does not give data immediately after the HLS module is ready to accept data.

When you use the IP in your own RTL, as soon as ap_ready is asserted, you can send new data to it to achieve II=28.
 
AR# 60472
Date Created 04/30/2014
Last Updated 03/23/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.1