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AR# 60528

MIG UltraScale DDR3/DDR4 - Vivado may fail to generate output products with 64-bit data width


Version Found: v5.0
Version Resolved: See (Xilinx Answer 58435)

When generating MIG DDR3 or DDR4 64-bit data width designs the following error messages might be seen when generating the output products:

ERROR: [#UNDEF] There are certain ports which are still unassigned as per the selected data width 64, design generation can be done correctly once all the bytes/sites are assigned.


This is a known issue where the Addr/Ctrl-2 byte group is not being placed into a byte lane in the Bank Planning page of the MIG GUI.

To work around the issue, manually select each byte lane including Addr/Ctrl-2 in the Bank Planning page.

In some cases, it may also be necessary to place additional scalar pins and the differential system clock (sys_clk) using the I/O Planner on the next page of the MIG GUI.

Revision History
05/05/2014 - Initial release
11/18/2014 - Added DDR4 to description and title

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 60528
Date 11/26/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale