Version Found: DDR4 v5.0, DDR3 v5.0
When generating MIG DDR3 or DDR4 64-bit data width designs, the following error messages might be seen when generating the output products:
This is a known issue where the Addr/Ctrl-2 byte group is not being placed into a byte lane in the Bank Planning page of the MIG GUI.
To work around the issue, manually select each byte lane including Addr/Ctrl-2 in the Bank Planning page.
In some cases, it might also be necessary to place additional scalar pins and the differential system clock (sys_clk) using the I/O Planner on the next page of the MIG GUI.