AR# 60528


UltraScale DDR4/DDR3 - Vivado might fail to generate output products with 64-bit data width


Version Found: DDR4 v5.0, DDR3 v5.0

See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

When generating MIG DDR3 or DDR4 64-bit data width designs, the following error messages might be seen when generating the output products:

ERROR: [#UNDEF] There are certain ports which are still unassigned as per the selected data width 64, design generation can be done correctly once all the bytes/sites are assigned.


This is a known issue where the Addr/Ctrl-2 byte group is not being placed into a byte lane in the Bank Planning page of the MIG GUI.

To work around the issue, manually select each byte lane including Addr/Ctrl-2 in the Bank Planning page.

In some cases, it might also be necessary to place additional scalar pins and the differential system clock (sys_clk) using the I/O Planner on the next page of the MIG GUI.

Revision History

  • 05/05/2014 - Initial release
  • 11/18/2014 - Added DDR4 to description and title

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 60528
Date 03/26/2018
Status Active
Type Known Issues
Tools More Less
People Also Viewed