Generating the GTZ example design in the 7 Series FPGAs Transceivers Wizard returns the following error message:
The implementation flow will continue in spite of the error.
Can this error message be ignored safely?
Before the opt_design step, v7ht.tcl is sourced twice.
This error is caused by the LOCK_PINS contained in v7ht.tcl being executed twice.
Because the LOCK_PINS property is set correctly, the error message can be ignored safely.
The issue where v7ht.tcl is read twice is fixed in Vivado 2014.2.