This is a known issue to be fixed in a future release of the core.
To work around this issue in the current release, make the following modification in project/pcie_7x_0_example/pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/simulation/dsport/xilinx_pcie_2_1_rport.7x.v :
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
07/31/2014 - Initial Release