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AR# 60671

2014.1 SDK: BSP standalone v4.0 Xil_DCacheInvalidateRange boundary check issues cause more cachelines to be invalidated

Description

This issue arises in the standalone_v4_0 BSP in Vivado Design Suite 2014.1.

The "Xil_DCacheInvalidateRange" API in src/cortexa9/xil_cache.c is invalidating one extra cache line than needed due to improper cache line calculation.

This can sometimes cause unexpected failures or behavior.

For example, if Xil_DCacheInvalidateRange (unsigned int adr, unsigned len) is provided with adr==0x100 and len==0x20 it will invalidate two cache lines (starting from 0x100 until 0x11f and 0x120 until 0x13f).

In previous versions it was correctly invalidating only one (from 0x100 to 0x11f).

Solution

This issue has been fixed in SDK 2014.2 with a new version of standalone BSP, standalone_v4_1.

To work around this issue in Vivado 2014.1/XPS 14.7 download the attached zip.

Inside the zip there is a standalone BSP for both XPS, and Vivado.

XPS flow:

SDK -> Xilinx Tools -> Repository. Select New, and navigate to the "xps" folder in the attached zip

Vivado flow:

SDK -> Xilinx Tools -> Repository. Select New, and navigate to the "vivado" folder in the attached zip

Note: If using a pre-existing project, you should re-build the BSP (Project -> Clean, and Build All) to detect the new changes.

Attachments

Associated Attachments

Name File Size File Type
ar60671.zip 1 MB ZIP
AR# 60671
Date Created 05/15/2014
Last Updated 07/02/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2014.1