UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60693

Zynq-7000 AP SoC, I2C - Fast Mode running faster than 384kHz violates tLOW; STA timing requirement

Description

The I2C controller violates the tLOW; STA timing parameter when it is running in Fast Mode and the controller operates above 384 kHz.
.
The tLOW parameter relates to the LOW period of the SCL clock.

Solution

The I2C controller violates the I2C-bus specification 1.3 us minimum requirement on tLOW  during Fast-mode when it runs above 384 kHz.
 
The max SCL clock frequency of the I2C Fast-mode is specified as 400 kHz..

This erratum limits the max frequency of the SCL which has a direct ratio with the tLOW to be limited to 384 kHz.

At this frequency tLOW is at its minimum specified value of 1.3 us.

This issue affects only devices that use the I2C Fast-mode.
 
Impact:  

Minor. The tLOW time of the I2C controller operating at 400 kHz is 1.25 us.

The latest I2C devices can typically recognize a tLOW time of 1.25 us.
 
Work-around: 

There are 2 work-around for this issue:
 
  • Run I2C below 384 kHz in Fast-mode.
  • Assume a tLOW of 1.25 us in the design instead of 1.3 us, if SCL frequency of 400 kHz is required.
Configurations Affected:
     
All Zynq devices using I2C Fast-mode.
 
Device Revision(s) Affected:

All, no plan to fix.
Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.

Resolution:


This is a third-party errata. This issue will not be fixed.
 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 60693
Date Created 05/16/2014
Last Updated 08/08/2014
Status Active
Type Design Advisory
Devices
  • SoC