the I2C-bus specification has a 1.3 us minimum requirement on tBUF (bus free time between a STOP and START condition).
The I2C controller violates this specification during Fast-mode when it runs above 384 kHz..
The max SCL clock frequency of the I2C Fast-mode is specified as 400 kHz.
This erratum corrects the limit on the max frequency of an SCL which has a direct ratio with the tBUF to 384 kHz.
At this frequency tBUF is at its minimum specified value of 1.3 us.
This issue only affects devices that use the I2C Fast-mode.
Note: The SCL frequency and tBUF depend on the internal bus frequency and the divider values in the I2C Controller in the PS.
Please refer to the Zynq TRM for detail programming guideline.
The tBUF time of the I2C controller operating at 400 kHz is 1.25 us.
The latest I2C devices can typically accept a tBUF time of 1.25 us.
There are 3 work-around for this issue.
- Run I2C below 384 kHz in Fast-mode.
- Assume a tBUF of 1.25 us in the design instead of 1.3 us, if SCL frequency of 400 kHz is required.
- For single master systems, update the driver to ensure transaction does not START until 1.3 us after a STOP condition.
All Zynq devices using I2C Fast-mode.
Device Revision(s) Affected:
All, no plan to fix.
Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences
This is a third-party errata, this issue will not be fixed.