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AR# 60703

2014.1 - How can I simulate a hierarchial submodule in a IP Integrator Block Design


Is it possible to simulate one hierarchical sub-module only within a bigger IPI block Design?


Yes, this is possible.

In some situations, it is useful to isolate a sub-section of an IPI block design, as shown in the flow below which contains a custom divider IP:



Follow the steps below to simulate just the clocking_system hierarchy.

First, generate the Output Products.

Next, create a testbench and instantiate this sub-module.

In Sources view, expand the hierarchy below the Block Design to find the instantiation of the hierarchy that is to be simulated.

The hierarchy will also show the unique component/module name which IP Integrator assigns to that hierarchy.

In the example below, the clocking_system hierarchy is to be simulated, and the unique component/module name given is "clocking_system_imp_L19ZY3":



The example testbench showing the instantiation is seen below:




Before simulating the design, set the Hierarchy Update to Automatic Update, Manual Compile Order. 

This tells the Vivado tool to compile all sources regardless of if the tool believes the source is needed.



Next, simulate the design.


Note: To simulate a hierarchical system containing a Microblaze the user will first need to generate the MEM file(s). 

This can be done by running simulation on the complete system and copying the MEM files from the behav folder into a separate location. 

Once this is done the MEM file(s) can be added to simulation sources and the hierarchical system containing the Microblaze can be simulated.


AR# 60703
Date 06/03/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.1