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AR# 60707

JESD204 - Vivado 2013.4 and earlier - GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover

Description

When using JESD v5.0 and earlier, production reset GTP and GTH DRP sequence can end up in a hung state that requires reconfiguration to recover (Xilinx Answer 60489) 

The failure is only seen when a second reset is issued to the core while a previous reset sequence is underway.  

The reset sequence is started automatically after configuration, so this could happen if the main core reset is toggled shortly after the device is configured.  

The failure happens due to a DRP register setting getting stuck with a 16-bit Rx data width instead of the required 20-bit data width.  

JESD204 uses a 20-bit data width during normal operation, but DRP logic sets data width to16-bit during a reset sequence to avoid production reset issues (see the GT Transceiver User Guide for more information on required reset logic).   

The failure is only seen when a second reset is issued to the core while a previous reset sequence is underway.

Solution

To work around this, the second DRP write can be changed to ensure that the data width is set back to 20 instead of relying on the initially read value which can get stuck at 16, if a reset is issued during the DRP sequence.  

The DRP update should be made to <core_name>_*_gtrxreset_seq.v/vhd

(If used also change <core_name>_*_gtrxrate_seq.v/vhd and <core_name>_*_ gtrxpmarst_seq.v/vhd ).
 
For VHDL change the following: 

      --write to 20-bit mode
      WHEN wr_20 =>  
        ....
        drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
To:
      --write to 20-bit mode
      WHEN wr_20 =>
        ...
         drpdi_o <= rd_data(15 downto 12) & '1' & rd_data(10 downto 0); --restore 20-bit mode


For Verilog change the following:
//write to 20-bit mode
                wr_20 : begin
                        ....
                        drpdi_o = rd_data[15:0]; //restore user setting per prev read
                end
To:
//write to 20-bit mode
                wr_20 : begin
                         ....
                        drpdi_o = {rd_data[15:12], 1'b1, rd_data[10:0]}; //restore 20-bit
                end
AR# 60707
Date Created 05/16/2014
Last Updated 10/23/2014
Status Active
Type General Article
IP
  • JESD204