Why do the post implementation/post synthesis simulation results of the G.709 FEC Decoder vary from the behavioral simulation results in 2014.2 when the simulation language is VHDL?
The Behavior simulation is correct. This is a known issue affecting VHDL only.
It is restricted to cases using the Decoder and affects only UltraScale devices.
The workaround is to use Verilog as the simulation language.
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