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  3. AR# 60755: Zynq-7000 AP SoC – 2014.1 Boot failed when EMIO TPIU is enabled

AR# 60755

Zynq-7000 AP SoC – 2014.1 Boot failed when EMIO TPIU is enabled

Description

QSPI/SD booting fails when EMIO TPIU is enabled.

I enabled DEBUG_FSBL_INFO, but there is no message outputted.

Also JTAG cannot be connected via XMD.

Why does this happen and what is the work-around?

Solution

When EMIO TPIU is enabled, external input clock can be select for TRACE_CLK by setting bit6 of DBG_CLK_CTRL.

However there is a limitation that PL must be powered and configured before setting the TPIU register.

During the QSPI/SD boot, FSBL switches TRACE_CLK to EMIO and after that it writes into the TPIU CurrentSize register (0xf8803004).

This causes the system to hang, because there is no active clock input to the Debug sub-system.   

This register write is NOT necessary and the debugger can change the CurrentSize after the system is up and running.

To resolve this issue comment out the write to 0xf8803004 in the ps7_init.c file.
AR# 60755
Date 06/16/2014
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2014.1
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit
  • Zynq-7000 All Programmable SoC ZC706 Evaluation Kit