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AR# 60772

2014.2 Vivado - Language template comments for IDELAYE3 of Kintex/Virtex Ultrascale device are incorrect

Description

When I open the content of IDELAYE3 for a Kintex/Virtex UltraScale device in language template, (Verilog(VHDL) -> Device Primitive Instantiation -> Kintex/Virtex UltraScale -> I/O -> DELAY -> IDELAYE3),

I can see the following:

   IDELAYE3 #(
      .CASCADE("NONE"),         // Cascade setting (NONE, MASTER, SLAVE_END, SLAVE_MIDDLE)
      .DELAY_FORMAT("TIME"),    // Units of the DELAY_VALUE (TIME, COUNT)
      .DELAY_SRC("IDATAIN"),    // Delay input (IDATAIN, DATAIN)
      .DELAY_TYPE("FIXED"),     // Set the type of tap delay line (FIXED, VAR_LOAD, VARIABLE)
      .DELAY_VALUE(0),          // Input delay value setting
      .IS_CLK_INVERTED(1'b0),   // Optional inversion for CLK
      .IS_RST_INVERTED(1'b0),   // Optional inversion for RST
      .REFCLK_FREQUENCY(300.0), // IDELAYCTRL clock input frequency in MHz (VALUES)
      .UPDATE_MODE("ASYNC")     // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
   )
   IDELAYE3_inst (
      .CASC_OUT(CASC_OUT),       // 1-bit output: Cascade delay output to ODELAY input cascade
      .CNTVALUEOUT(CNTVALUEOUT), // 9-bit output: Counter value output
      .DATAOUT(DATAOUT),         // 1-bit output: Delayed data output
      .CASC_IN(CASC_IN),         // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
      .CASC_RETURN(CASC_RETURN), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
      .CE(CE),                   // 1-bit input: Active high enable increment/decrement input
      .CLK(CLK),                 // 1-bit input: Clock input
      .CNTVALUEIN(CNTVALUEIN),   // 9-bit input: Counter value input
      .DATAIN(DATAIN),           // 1-bit input: Data input from the IOBUF
      .EN_VTC(EN_VTC),           // 1-bit input: Keep delay constant over VT
      .IDATAIN(IDATAIN),         // 1-bit input: Data input from the logic
      .INC(INC),                 // 1-bit input: Increment / Decrement tap delay input
      .LOAD(LOAD),               // 1-bit input: Load DELAY_VALUE input
      .RST(RST)                  // 1-bit input: Asynchronous Reset to the DELAY_VALUE
   );

  
But for the ports IDATAIN and DATAIN, the correct comment should be :

      .DATAIN(DATAIN),          // 1-bit input: Data input from the logic
      .IDATAIN(IDATAIN),        // 1-bit input: Data input from the IOBUF 

 

 

 

Solution

This will be fixed in Vivado release 2014.3.


The correct template for IDELAYE3 should be as follows :


   IDELAYE3 #(
      .CASCADE("NONE"),         // Cascade setting (NONE, MASTER, SLAVE_END, SLAVE_MIDDLE)
      .DELAY_FORMAT("TIME"),    // Units of the DELAY_VALUE (TIME, COUNT)
      .DELAY_SRC("IDATAIN"),    // Delay input (IDATAIN, DATAIN)
      .DELAY_TYPE("FIXED"),     // Set the type of tap delay line (FIXED, VAR_LOAD, VARIABLE)
      .DELAY_VALUE(0),          // Input delay value setting
      .IS_CLK_INVERTED(1'b0),   // Optional inversion for CLK
      .IS_RST_INVERTED(1'b0),   // Optional inversion for RST
      .REFCLK_FREQUENCY(300.0), // IDELAYCTRL clock input frequency in MHz (VALUES)
      .UPDATE_MODE("ASYNC")     // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
   )
   IDELAYE3_inst (
      .CASC_OUT(CASC_OUT),       // 1-bit output: Cascade delay output to ODELAY input cascade
      .CNTVALUEOUT(CNTVALUEOUT), // 9-bit output: Counter value output
      .DATAOUT(DATAOUT),         // 1-bit output: Delayed data output
      .CASC_IN(CASC_IN),         // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
      .CASC_RETURN(CASC_RETURN), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
      .CE(CE),                   // 1-bit input: Active high enable increment/decrement input
      .CLK(CLK),                 // 1-bit input: Clock input
      .CNTVALUEIN(CNTVALUEIN),   // 9-bit input: Counter value input
      .DATAIN(DATAIN),           // 1-bit input: Data input from the logic
      .EN_VTC(EN_VTC),           // 1-bit input: Keep delay constant over VT
      .IDATAIN(IDATAIN),         // 1-bit input: Data input from the IOBUF
      .INC(INC),                 // 1-bit input: Increment / Decrement tap delay input
      .LOAD(LOAD),               // 1-bit input: Load DELAY_VALUE input
      .RST(RST)                  // 1-bit input: Asynchronous Reset to the DELAY_VALUE
   );

 

 

AR# 60772
Date Created 05/21/2014
Last Updated 06/03/2014
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1