AR# 60802


UltraScale - How to calculate the size of TAP in IDELAY & ODELAY


In the Kintex UltraScale datasheet, the IDELAY_RESOLUTION/ODELAY_RESOLUTION value of the IDELAY3/ODELAY3 component is defined as 2.5 to 15 ps (The resolution over PVT, it is not dependent on the REFCLK).  

How do I calculate the TAP size?

If I am using the IDELAY3/ODELAY3 in VAR_LOAD mode how do I calculate what the value of CNTVALUEIN should be?


In the UltraScale devices the TAPs are calibrated over PVT when EN_VTC is high.

As with previous architectures there is an intrinsic delay when the IDELAYE3 is used, which accounts for the delay through the mux in the IDELAYE3.

This delay can be seen in Vivado timing when a DELAY_VALUE of 0 is used, regardless of the DELAY_FORMAT.

When setting the DELAY_VALUE remember that the total delay will equal the intrinsic delay. 


If the DELAY_FORMAT= TIME with a FIXED delay and EN_VTC is high then then that delay will be calculated according to the resolution of the taps of the used device.

For example if the delay is set to 800ps then the IDELAY ensures that the correct amount of taps are set to get 800ps (+ the intrinsic delay). This is done in the BITSLICE_CONTROL (even when using component mode and no BITSLICE_CONTROL is instantiated). 

The BITSLICE_CONTROL will calculate that value after measuring the tap delay, so the number of taps in the delay chain can be 320 taps or 53 taps. If EN_VTC is low then the delay will not be compensated for V and T. 

If using TIME mode it is possible that the delay could be a number of times bigger or smaller than the requested DELAY_VALUE.

If using COUNT mode then the delay will vary by the amount of taps used multiplied by the resolution. *** As described above the Tap size can vary between 2.5 to 15 ps across PVT independant of the REFCLK. 


If the DELAY_TYPE is VAR_LOAD, then as the TAP size varies over VT you will need to read the CNTVALUEOUT to calculate the current value of the TAP and use this to calculate how many TAPs are required for the new delay. 

To calculate what the CNTVALUEIN should be, use the following procedure:

  1. Start with EN_VTC = 1
  2. Program initial DELAY_VALUE to be a non-zero FIXED value, DLY0
  3. In order to switch to the new DELAY, DLY1 using the VAR_LOAD mode do the following:

    • De-assert EN_VTC. Wait 10 CLKDIV cycles.
    • Wait 10 CLKDIV cycles. Re-assert EN_VTC


The delay line has a minimum of 512taps*2.5ps = 1280ps. 

The Maximum is 512taps*15ps = 7.68ns.

Cascading can be used to achieve delays greater than 1.25ns.

If using cascading to achieve a DELAY > 1.25ns with a DELAY_FORMAT = TIME, delays in the same site must have an equal delay.

For example, for a 1.5ns delay the split should be 0.75 in the IDELAY and 0.75 in the ODELAY.

If a CASCADE of IDELAY-ODELAY is used in VAR_LOAD mode, the values will need to be entered for both components separately. 

The sequence detailed above must be done for the IDELAY and also for the ODELAY. 

The TAP size for IDELAY/ODELAY and in a MASTER/SLAVE pair are comparable.

Supported DELAY_TYPE and DELAY_FORMAT combinations:

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
64743 UltraScale IODELAY - What is the clock alignment delay N/A N/A
AR# 60802
Date 06/14/2017
Status Archive
Type General Article
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