AR# 60810

MIG UltraScale DDR4 - Data mismatch errors seen when simulating MIG DDR4 core with Micron simulation memory model

Description

Version Found: MIG v5.0
Version Resolved: See (Xilinx Answer 58435)

When simulating the MIG UltraScale DDR4 core with the encrypted DDR4 Micron model, the model is not latching the write data on the current cycle but rather on the next CK cycle.

This causes the data to be written on the wrong cycle and as a result read data errors are seen in simulation.

Specifically, Xs will be seen at the end of the read.

This has been seen on all MIG supported simulators.

Solution

This issue is under investigation.

During this time, manual workarounds to the testbench are required.

Step 1

This answer record includes a modified MIG texbench that works around the timing error.

The testbench attached is for a default MIG configuration.

Therefore, the parameters and port widths of the generated testbench should be copied to the attached testbench.

The manual steps to do this are as follows:

Download the attached "sim_tb_top.sv" module.
Copy all localparam values from the generated MIG "sim_tb_top.sv" testbench located in the "sim_1/imports/core_name/tb" directory of a generated MIG IP Example Design to the attached module.
Update the port widths on lines 117-120 in the testbench attached to this AR to match the widths used in the MIG generated testbench.
Modify the added ports' widths on lines 124-131.
Update the sys_clk assignment on line 154 to use the input clock period set during core generation.
Note: the value that should be used can be found in the localparam assignment of CLKIN_PERIOD_NS on line 93.
As an example, the module provided uses the following:
```
sys_clk_i = #(14045/2.0) ~sys_clk_i;
```
The input clock for this design is 14045. This should be modified according to the value used during MIG core generation.
Update the instance names on line 186 to match the core name assigned during core generation.
Modify the instance name on line 228 from: mig_v6_0_ddr4_traffic_generator to mig_v5_0_ddr4_traffic_generator

To manually work around this within a user testbench (not the MIG generated testbench), delays must be added to the write DQ, DM, and DQS to delay the signal transitions until the next cycle of CK.

The models perform the write correctly if the write DQ and DM are delayed to be available until the CK cycles associated with the 8th DQS.

Below is an example of the delay added (see bold # delays) to the MIG testbench.

Similar modifications should be made to the user testbench.

   assign #((tCK/4) - 90) c0_ddr4_dq_mem = (wr_en == 1'b1) ? c0_ddr4_dq_dut : 'bz ;
   assign c0_ddr4_dm_dbi_n_dut = (wr_en == 1'b1) ? 'bz : c0_ddr4_dm_dbi_n_mem ;
   assign #((tCK/4) - 90) c0_ddr4_dm_dbi_n_mem = (wr_en == 1'b1) ? {DM_WIDTH{1'b1}} : 'bz ;
   assign c0_ddr4_dq_dut = (wr_en == 1'b1) ? 'bz : c0_ddr4_dq_mem ;
   assign c0_ddr4_dqs_t_dut = (wr_en == 1'b1) ? 'bz : c0_ddr4_dqs_t_mem ;
   assign #100 c0_ddr4_dqs_t_mem = (wr_en == 1'b1) ? c0_ddr4_dqs_t_dut : 'bz ;
   assign c0_ddr4_dqs_c_dut = (wr_en == 1'b1) ? 'bz : c0_ddr4_dqs_c_mem ;
   assign #100 c0_ddr4_dqs_c_mem = (wr_en == 1'b1) ? c0_ddr4_dqs_c_dut : 'bz ;

Step 2
To resolve Xs that will be seen on c0_ddr4_dm_dbi_n_dut, modify the wire declaration of c0_ddr4_app_wdf_mask within the sim_tb_top.sv testbench to be the width of app_wdf_data/8.

For example, a 32-bit DDR4 interface will have an app_wdf_data width of 256.

This would require a c0_ddr4_app_wdf_mask width of 32:

   wire [31:0]                       c0_ddr4_app_wdf_mask;

Additional Information:
See (Xilinx Answer 60876) MIG UltraScale DDR4 - License agreement and generation of encrypted Micron DDR4 simulation model

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Associated Attachments

Name	File Size	File Type
sim_tb_top.sv	17 KB	SV

AR# 60810
Date	07/04/2014
Status	Active
Type	General Article
Devices	Kintex UltraScale Virtex UltraScale
IP	MIG UltraScale

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AR# 60810

MIG UltraScale DDR4 - Data mismatch errors seen when simulating MIG DDR4 core with Micron simulation memory model

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