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AR# 60821

Vivado 2014.2 - Zynq-7000 Example Design - Cache coherent CDMA transfers from block RAM to OCM

Description

This example design allocates 4K of block RAM attached to the CPU via M_AXI_GP0.

The same block RAM is also accessible by the CDMA.

The CPU initializes the block RAM. The CDMA in simple mode is transferring data from the block RAM to the OCM via ACP port.

The transfer is cache coherent and when the transfer is complete, the CPU sees the updated OCM without invalidating or flushing the cache.

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.

Limited support is provided by Xilinx on these Example Designs.

Solution

Implementation Details

Design Type

PS and PL

SW Type

Standalone

CPUs

Single CPU @ 667MHz

PS Features

MMU, OCM

PL Cores

BRAM, CDMA

Boards/Tools

ZC702

Xilinx Tools Version

Vivado 2014.2

Other details

FCLK @ 50MHz

Address Map






Files Provided

cdma_acp_design.zip

 Archived Vivado project.

cdma_acp_bd.tcl

TCL file to create the block design.

hello_axi_cdma.c

Snippet of code.

 Block Diagram

 





 

Step-by-Step Instructions

  1. Import the archived design into Vivado and export to SDK.(Or you can create a ZC702 board based design and run cdma_acp_bd.tcl to create the block design)
  2. In SDK, create an Empty Application example.
  3. Import the included snippet of C code.
  4. Program the PL using the BITSTREAM generated by Vivado.
  5. Run the application.

Important Notes

  1. The HIGH OCM must be accessible through the ACP port.

  2. The MMU table has the HIGH OCM shareable.

          /* S=b1 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
          Xil_SetTlbAttributes(0xFFF00000,0x10C06);

Expected Results

On the Terminal, at the end of the test, the destination memory should match the source memory.

The CPU can see the data transferred by the CDMA without any particular software implemented. 

Attachments

Associated Attachments

Name File Size File Type
cdma_acp_bd.tcl 10 KB TCL
hello_axi_cdma.c 4 KB C
cdma_acp_design.zip 13 MB ZIP

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
50826 Zynq-7000 Example Design - Cache coherent CDMA transfers from block RAM to OCM N/A N/A
AR# 60821
Date Created 05/26/2014
Last Updated 03/25/2015
Status Active
Type General Article
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit